1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and method for fabricating the same and, more particularly, to a TFT formed by a Metal Induced Lateral Crystallization (MILC) process and method for fabricating the same.
2. Discussion of the Related Art
A method for forming a polycrystalline silicon layer, which may be used for the TFT's active layer, comprises depositing an amorphous silicon layer on an insulating substrate, and then crystallizing the amorphous silicon layer at a predetermined temperature.
Solid Phase Crystallization (SPC), Eximer Laser Annealing (ELA), Metal Induced Lateral Crystallization (MILC), and other similar methods may be employed to crystallize the amorphous silicon layer.
However, the SPC method takes a long time, and it requires a high temperature for the crystallization. The ELA method requires expensive equipment, and the laser may cause unevenness and striped defects.
However, the MILC method requires a relatively low processing temperature and a short time for the process, and conventional thermal treatment equipment may be used.
FIG. 1 is a plan view showing an active layer and a gate electrode of a conventional TFT.
The TFT shown in FIG. 1 comprises an active layer 110 crystallized by the MILC process and having source/drain regions S and D, a gate electrode 120, and contact holes 130 for exposing portions of the source/drain regions S and D.
FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D are cross-sectional views showing a method for fabricating a conventional TFT, which are taken along the line I–I′ of FIG. 1.
Referring to FIG. 2A, amorphous silicon is deposited on an insulating substrate 200 having a buffer layer 210 and patterned to form an amorphous silicon active layer 220.
After the forming the active layer 220, a gate insulating layer 230 and a gate electrode material are sequentially formed on the substrate, and the gate electrode material is then patterned to form a gate electrode 240.
Next, impurities are implanted using the gate electrode 240 as a mask to form source/drain regions 221 and 225 in the active layer 220. A region between the source/drain regions 221 and 225 acts as a channel region 223.
Referring to FIG. 2B, an interlayer insulating layer 250 is deposited on the substrate having the gate electrode 240, and contact holes 251 and 255 are then formed to expose portions of the source/drain regions 221 and 225.
A crystallization inducing metal layer 260, such as nickel (Ni), is then deposited on the substrate by means of sputtering or other similar methods.
Referring to FIG. 2C, the crystallization inducing metal layer 260 is heat treated in a furnace to crystallize the amorphous silicon active layer 220 into a polycrystalline silicon layer.
Amorphous silicon regions 221a and 225a,located below the crystallization inducing metal layer 260 and within the contact holes 251 and 255, are crystallized by a metal induced crystallization (MIC) process, and the remaining amorphous silicon regions 221b and 225b are crystallized by the MILC process.
Referring to FIG. 2D, the crystallization inducing metal layer 260 is removed, and a conductive layer is deposited and patterned to form source/drain electrode 271 and 275, thus forming the TFT.
In the TFT fabricated by the above-mentioned process, contact holes may have different sizes to lack of etch uniformity of HF, which may be used for a general etchant during the process of forming the contact holes 251 and 255. Additionally, a contact hole exposes a small portion of the active layer as compared to the total width of the active layer.
The small and irregular contact hole size may cause a lack of uniformity of crystallization speed and a lowered crystallization speed while performing the MILC process. Consequently, the TFT's characteristics may not be constant.